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FEATURES Fast 16-Bit ADC with 200 kSPS Throughput Four Single-Ended Analog Input Channels Single +5 V Supply Operation Input Ranges: 0 V to +4 V, 0 V to +5 V and 10 V 120 mW Max Power Dissipation Power-Down Mode 50 W Choice of External or Internal 2.5 V Reference On-Chip Clock Power-Down Mode
V1A V1B
4-Channel, 16-Bit, 200 kSPS Data Acquisition System AD974
FUNCTIONAL BLOCK DIAGRAM
PWRD BIP CAP REF VDIG VANA
REF BUFF RESISTIVE NETWORK
2.5V REFERENCE
AD974
EXT/INT SWITCHED 16 CAP ADC DATACLK SERIAL INTERFACE DATA R/C CS CLOCK SYNC
V2A V2B
RESISTIVE NETWORK 4 TO 1 MUX + LATCH
V3A V3B
RESISTIVE NETWORK
V4A V4B
RESISTIVE NETWORK
EN CONTROL LOGIC & CALIBRATION CIRCUITRY
GENERAL DESCRIPTION
The AD974 is a four-channel, data acquisition system with a serial interface. The part contains an input multiplexer, a highspeed 16-bit sampling ADC and a +2.5 V reference. All of this operates from a single +5 V power supply that also has a powerdown mode. The part will accommodate 0 V to +4 V, 0 V to +5 V or 10 V analog input ranges. The interface is designed for an efficient transfer of data while requiring a low number of interconnects. The AD974 is comprehensively tested for ac parameters such as SNR and THD, as well as the more traditional parameters of offset, gain and linearity. The AD974 is fabricated on Analog Devices' BiCMOS process, which has high performance bipolar devices along with CMOS transistors. The AD974 is available in 28-lead DIP, SOIC and SSOP packages.
AGND1 AGND2
A0 A1 WR1 WR2
BUSY
DGND
PRODUCT HIGHLIGHTS
1. The AD974 is a complete data acquisition system combining a four-channel multiplexer, a 16-bit sampling ADC and a +2.5 V reference on a single chip. 2. The part operates from a single +5 V supply and also has a power-down feature. 3. Interfacing to the AD974 is simple with a low number of interconnect signals. 4. The AD974 is comprehensively specified for ac parameters such as SNR and THD, as well as dc parameters such as linearity and offset and gain errors.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD974-SPECIFICATIONS (-40 C to +85 C, f = 200 kHz, V
S
DIG
= VANA = +5 V, unless otherwise noted)
Min 16 B Grade Typ Max Units Bits
Parameter RESOLUTION ANALOG INPUT Voltage Range Impedance Sampling Capacitance THROUGHPUT SPEED Complete Cycle (Acquire and Convert) Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise2 Full-Scale Error3 Full-Scale Error Drift Full-Scale Error Full-Scale Error Drift Bipolar Zero Error Bipolar Zero Error Drift Unipolar Zero Error Unipolar Zero Error Drift Channel-to-Channel Matching Recovery to Rated Accuracy After Power-Down4 Power Supply Sensitivity VANA = VDIG = VD AC ACCURACY Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Channel-to-Channel Isolation Full Power Bandwidth6 -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery7 REFERENCE Internal Reference Voltage Internal Reference Source Current External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH
Conditions
Min 16
A Grade Typ Max
Channel On or Off
10 V, 0 V to +4 V, 0 V to +5 V (See Table I) (See Table I) 40 40
pF
5 200 3 +3 1.0 Internal Reference Internal Reference Ext. REF = +2.5 V Ext. REF = +2.5 V Bipolar Range Bipolar Range Unipolar Ranges Unipolar Ranges 2.2 F to CAP VD = 5 V 5% fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz -60 dB Input fIN = 20 kHz fIN = 20 kHz 90 -90 83 27 83 -110 1 2.7 40 Full-Scale Step 150 2.48 2.3 Ext. REF = +2.5 V 2.5 1 2.5 2.52 2.7 100 2.48 2.3 1 150 2.5 1 2.5 -100 85 -110 1 2.7 40 85 28 7 2 2 2 1 8 96 0.5 0.5 10 10 0.1 200
5
s kHz LSB1 LSB Bits LSB % ppm/C % ppm/C mV ppm/C mV ppm/C % FSR ms
-2 15
-1 16 1.0 7 2 2 2 1
2.0 +1.75 0.25 0.25 10 10 0.05
8
LSB dB 5 dB dB dB dB dB MHz MHz ns s ns V A V A
-96
-100
1
2.52 2.7 100
-0.3 +2.0
+0.8 VDIG + 0.3 10 10
-0.3 +2.0
+0.8 VDIG + 0.3 10 10
V V A A
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AD974
Parameter DIGITAL OUTPUTS Data Format Data Coding VOL VOH Output Capacitance Leakage Current POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation PWRD LOW PWRD HIGH TEMPERATURE RANGE Specified Performance TMIN to TMAX Conditions Min A Grade Typ Max B Grade Min Typ Max Units Serial 16 Bits Straight Binary +0.4 +4 15 5
ISINK = 1.6 mA ISOURCE = 500 A High-Z State High-Z State VOUT = 0 V to V DIG
+0.4 15 5
+4
V V pF A
+4.75 +4.75
+5 +5 4.5 14 50
+5.25 +5.25
+4.75 +5 +4.75 +5 4.5 14 50
+5.25 +5.25
V V mA mA mW W C
120
120
-40
+85
-40
+85
NOTES 1 LSB means Least Significant Bit. With a 10 V input, one LSB is 305 V. 2 Typical rms noise at worst case transitions and temperatures. 3 Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect of offset error. For bipolar input, the Full-Scale Error is the worst case of either the -Full-Scale or +Full-Scale code transition voltage errors. For unipolar input ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage. 4 External 2.5 V reference connected to REF. 5 All specifications in dB are referred to a full-scale 10 V input. 6 Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy. 7 Recovers to specified performance after a 2 x FS input overvoltage. Specifications subject to change without notice.
TIMING SPECIFICATIONS (f = 200 kHz, V
S
DIG
= VANA = +5 V, -40 C to +85 C)
Min 50 100 4.0 50 40 3.8 1.0 5 220 220 50 20 66 20 30 20 10 15 25 10 3.5 5 10 10 50 Typ Max Units ns ns s ns ns s s s ns ns ns ns ns ns ns ns ns ns ns ns s ns s ns ns ns
Parameter Convert Pulsewidth R/C, CS to BUSY Delay BUSY LOW Time BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Throughput Time R/C Low to DATACLK Delay DATACLK Period DATA Valid Setup Time DATA Valid Hold Time EXT. DATACLK Period EXT. DATACLK HIGH EXT. DATACLK LOW R/C, CS to EXT. DATACLK Setup Time R/C to CS Setup Time EXT. DATACLK to SYNC Delay EXT. DATACLK to DATA Valid Delay CS to EXT. DATACLK Rising Edge Delay Previous DATA Valid after CS, R/C Low BUSY to EXT. DATACLK Setup Time Final EXT. DATACLK to BUSY Rising Edge A0, A1 to WR1, WR2 Setup Time A0, A1 to WR1, WR2 Hold Time WR1, WR2 Pulsewidth
Specifications subject to change without notic e.
Symbol t1 t2 t3 t4 t5 t6 t7 t6 + t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25
4.0
t12 + 5 66 66
1.7
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AD974
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION SOIC, DIP AND SSOP
Analog Inputs VxA, VxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V CAP . . . . . . . . . . . . . . . . +VANA + 0.3 V to AGND2 - 0.3 V REF . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . 0.3 V Supply Voltages VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Digital Inputs . . . . . . . . . . . . . . . . . . . -0.3 V to VDIG + 0.3 V Internal Power Dissipation2 PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150C Storage Temperature Range N, R . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 28-Lead PDIP: JA = 100C/W, JC = 31C/W 28-Lead SOIC: JA = 75C/W, JC = 24C/W 28-Lead SSOP: JA = 109C/W, JC = 39C/W
AGND1 1 V3A 2 V3B 3 V4A 4 V4B 5 BIP 6 CAP 7
28 27 26 25 24
V2B V2A V1B V1A VANA A0
AD974
23
TOP VIEW 22 A1 REF 8 (Not to Scale) 21 BUSY
20 19 18 17 16 15
AGND2 9 R/C 10 VDIG 11 PWRD 12 EXT/INT 13 DGND 14
CS WR1 WR2 DATA DATACLK SYNC
1.6mA
IOL
TO OUTPUT PIN
+1.4V CL 100pF 500 A IOH
Figure 1. Load Circuit for Digital Interface Timing
ORDERING GUIDE
Model AD974AN AD974BN AD974AR AD974BR AD974ARS AD974BRS
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Max INL 3.0 LSB 2.0 LSB 3.0 LSB 2.0 LSB 3.0 LSB 2.0 LSB
Min S/(N+D) 83 dB 85 dB 83 dB 85 dB 83 dB 85 dB
Package Description 28-Lead Plastic DIP 28-Lead Plastic DIP 28-Lead SOIC 28-Lead SOIC 28-Lead SSOP 28-Lead SSOP
Package Options N-28B N-28B R-28 R-28 RS-28 RS-28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD974 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD974
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2-5, 25-28 6 7 8
Mnemonic AGND1 VxA, VxB BIP CAP REF
Description Analog Ground. Used as the ground reference point for the REF pin. Analog Input. Refer to Table I for input range configuration. Bipolar Offset. Connect VxA inputs to provide Bipolar input range. Reference Buffer Output. Connect a 2.2 F tantalum capacitor between CAP and Analog Ground. Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively an external reference can be used to override the internal reference. In either case, connect a 2.2 F tantalum capacitor between REF and Analog Ground. Analog Ground. Read/Convert Input. Used to control the conversion and read modes. With CS LOW, a falling edge on R/C holds the analog input signal internally and starts a conversion; a rising edge enables the transmission of the conversion result. Digital Power Supply. Nominally +5 V. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited. The conversion result from the previous conversion is stored in the onboard shift register. Digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous conversion result as shown in Figure 3. With EXT/INT set to a Logic HIGH, output data is synchronized to an external clock signal connected to the DATACLK input. Data is output as indicated in Figure 4 through Figure 9. Digital Ground. Digital output frame synchronization for use with an external data clock (EXT/INT = Logic HIGH). When a read sequence is initiated, a pulse one DATACLK period wide is output synchronous to the external data clock. Serial data clock input or output, dependent upon the logic state of the EXT/INT pin. When using the internal data clock (EXT/INT = Logic LOW), a conversion start sequence will initiate transmission of 16 DATACLK periods. Output data is synchronous to this clock and is valid on both its rising and falling edges (Figure 3). When using an external data clock (EXT/INT = Logic HIGH), the CS and R/C signals control how conversion data is accessed. The serial data output is synchronized to DATACLK. Conversion results are stored in an onchip register. The AD974 provides the conversion result, MSB first, from its internal shift register. When using the internal data clock (EXT/INT = Logic LOW), DATA is valid on both the rising and falling edges of DATACLK. Using an external data clock (EXT/INT = Logic HIGH) allows previous conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the conversion result can be accessed after the completion of a conversion (Figures 4, 6 and 8). Multiplexer Write Inputs. These inputs are internally ORed to generate the mux latch inputs. The latch is transparent when WR1 and WR2 are tied low. Chip Select Input. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the serial data output sequence. Busy Output. Goes LOW when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the on-chip shift register. Address multiplexer inputs latched with the WR1, WR2 inputs. A1 0 0 1 1 A0 0 1 0 1 Data Available from Channel AIN 1 AIN 2 AIN 3 AIN 4
9 10
AGND2 R/C
11 12
VDIG PWRD
13
EXT/INT
14 15
DGND SYNC
16
DATACLK
17
DATA
18, 19 20 21 22, 23
WR1, WR2 CS BUSY A1, A0
24
VANA
Analog Power Supply. Nominally +5 V.
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AD974
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL) SPURIOUS FREE DYNAMIC RANGE
Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
FULL-SCALE ERROR
S/(N+D) is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
FULL POWER BANDWIDTH
The last + transition (from 011 . . . 10 to 011 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (9.9995422 V for a 10 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
BIPOLAR ZERO ERROR
The full power bandwidth is defined as the full-scale input frequency at which the S/(N+D) degrades to 60 dB, 10 bits of accuracy.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and is measured from the falling edge of the R/C input to when the input signal is held for a conversion.
TRANSIENT RESPONSE
Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
UNIPOLAR ZERO ERROR
The time required for the AD974 to achieve its rated accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point.
The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value.
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AD974
CONVERSION CONTROL INTERNAL DATA CLOCK MODE
The AD974 is controlled by two signals: R/C and CS. When R/C is brought low, with CS low, for a minimum of 50 ns, the input signal will be held on the internal capacitor array and a conversion "n" will begin. Once the conversion process does begin, the BUSY signal will go low until the conversion is complete. Internally, the signals R/C and CS are ORed together and there is no requirement on which signal is taken low first when initiating a conversion. The only requirement is that there be at least 10 ns of delay between the two signals being taken low. After the conversion is complete, the BUSY signal will return high and the AD974 will again resume tracking the input signal. Under certain conditions the CS pin can be tied Low and R/C will be used to determine whether you are initiating a conversion or reading data. On the first conversion, after the AD974 is powered up, the DATA output will be indeterminate. Conversion results can be clocked serially, using either an internal clock generated by the AD974 or an external clock. The AD974 is configured for the internal data clock mode by pulling the EXT/INT pin low. It is configured for the external clock mode by pulling the EXT/INT pin high.
The AD974 is configured to generate and provide the data clock when the EXT/INT pin is held low. Typically CS will be tied low and R/C will be used to initiate a conversion "n." During the conversion the AD974 will output 16 bits of data, MSB first, from conversion "n-1" on the DATA pin. This data will be synchronized with 16 clock pulses provided on the DATACLK pin. The output data will be valid on both the rising and falling edge of the data clock as shown in Figure 3. After the LSB has been presented, the DATACLK pin will stay low until another conversion is initiated. In this mode, the digital input/output pins' transitions are suitably positioned to minimize degradation on the conversion result, mainly during the second half of the conversion process.
EXTERNAL DATA CLOCK MODE
The AD974 is configured to accept an externally supplied data clock when the EXT/INT pin is held high. This mode of operation provides several methods by which conversion results can be read. The output data from conversion "n-1" can be read during conversion "n," or the output data from conversion "n"
t1
CS, R/C A0, A1
WR1, WR2
t23 t3
BUSY
t25
t24
t2 t5
MODE ACQUIRE CONVERT
t4
ACQUIRE CONVERT
t6
t7
Figure 2. Basic Conversion Timing
t8
R/C
t1
DATACLK 1
t9
2 3 15 16
t10
DATA
MSB VALID
t11
BIT 14 VALID BIT 13 VALID BIT 1 VALID LSB VALID
t2
BUSY
t6
Figure 3. Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS and EXT/ INT Set to Logic Low)
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AD974
can be read after the conversion is complete. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally low or normally high when inactive. In the case of the discontinuous clock, the AD974 can be configured to either generate or not generate a SYNC output (with a continuous clock a SYNC output will always be produced). Each of the methods will be described in the following sections and are illustrated in Figures 4 through 9. It should be noted that all timing diagrams assume that the receiving device is latching data on the rising edge of the external clock. If the falling edge of DATACLK is used then, in the case of a discontinuous clock, one less clock pulse is required than shown in Figures 4 through 7 to latch in a 16-bit word. Note that data is valid on the falling edge of a clock pulse (for t13 greater than t18) and the rising edge of the next clock pulse. The AD974 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion cycle. Normally the occurrence of an incorrect bit decision during a conversion cycle is irreversible. This error occurs as a result of noise during the time of the decision or due to insufficient settling time. As the AD974 is performing a conversion it is important that transitions not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion process. For this reason it is recommended that when an external clock is being provided it be a discontinuous clock that is not toggling during the time that BUSY is low or, more importantly, that it does not transition during the latter half of BUSY low.
t12 t13 t14
0 1 2 3 14 15 16
EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH NO SYNC OUTPUT GENERATED
Figure 4 illustrates the method by which data from conversion "n" can be read after the conversion is complete using a discontinuous external clock without the generation of a SYNC output. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. The MSB will be valid on the first falling edge and the second rising edge of DATACLK. The LSB will be valid on the 16th falling edge and the 17th rising edge of DATACLK. A minimum of 16 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 17 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. The advantage of this method of reading data is that data is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (15.15 MHz), the maximum possible throughput is approximately 195 kHz, and not the rated 200 kHz.
EXT DATACLK
t1
R/C
t2
BUSY
t21
SYNC DATA
t18 BIT 15
(MSB)
t18
BIT 14 BIT 13 BIT 1 BIT 0
(LSB)
Figure 4. Conversion and Read Timing Using an External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low)
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EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH NO SYNC OUTPUT GENERATED
Figure 5 illustrates the method by which data from conversion "n-1" can be read during conversion "n" while using a discontinuous external clock, without the generation of a SYNC output. After a conversion is initiated, indicated by BUSY going low, the result of the previous conversion can be read while CS is low and R/C is high. In this mode CS can be tied low. The MSB will be valid on the 1st falling edge and the 2nd rising edge of DATACLK. The LSB will be valid on the 16th falling edge and the 17th rising edge of DATACLK. A minimum of 16 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 17 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. In this mode the data should be clocked out during the first half of BUSY so not to degrade conversion performance. This requires use of a 10 MHz DATACLK or greater, with data being read out as soon as the conversion process begins.
EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED
discontinuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. In Figure 6 clock pulse #0 is used to enable the generation of a SYNC pulse. The SYNC pulse is actually clocked out approximately 40 ns after the rising edge of clock pulse #1. The SYNC pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. The advantage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (15.15 MHz), the maximum possible throughput is approximately 195 kHz and not the rated 200 kHz.
Figure 6 illustrates the method by which data from conversion "n" can be read after the conversion is complete using a
t12 t13
EXT DATACLK 0
t14
1 2 15 16
t15
R/C
t22
t1 t20
BUSY
t2
SYNC
t21 t18 t18
BIT 15 (MSB) BIT 14 BIT 0 (LSB)
DATA
Figure 5. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low)
t12 t13
EXT DATACLK 0 1 2
t14
3 4 17 18
t15
R/C
t15 t2
t15
BUSY SYNC
t17
t12 t18
DATA
BIT 15
(MSB)
t18
BIT 14 BIT 0
(LSB)
Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low)
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EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED
Figure 7 illustrates the method by which data from conversion "n-1" can be read during conversion "n" while using a discontinuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is High or while both CS and R/C are low. In Figure 7 a conversion is initiated by taking R/C low with CS tied low. While this condition exists a transition of DATACLK, clock pulse #0, will enable the generation of a SYNC pulse. Less then 83 ns after R/C is taken low the BUSY output will go low to indicate that the conversion process has
begun. Figure 7 shows R/C then going high and after a delay of greater than 15 ns (t15 ) clock pulse #1 can be taken high to request the SYNC output. The SYNC output will appear approximately 40 ns after this rising edge and will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid approximately 40 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. Data should be clocked out during the first half of BUSY to avoid degrading conversion performance. This requires use of a 10 MHz DATACLK or greater, with data being read out as soon as the conversion process begins.
t12 t13
EXT DATACLK 0 1 2
t14
3 4 17 18
t15
R/C
t15 t1
t22
t20
BUSY
t2
SYNC
t17 t12 t18 t18
BIT 14 BIT 0 (LSB) BIT 15 (MSB)
DATA
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low)
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EXTERNAL CONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED
Figure 8 illustrates the method by which data from conversion "n" can be read after the conversion is complete using a continuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK either while CS is high or while both CS and R/C are low. With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock. Use of a continuous clock, while a conversion is occurring, can increase the DNL and Transition Noise of the AD974. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is low
and R/C is high. In Figure 8 clock pulse #0 is used to enable the generation of a SYNC pulse. The SYNC pulse is actually clocked out approximately 40 ns after the rising edge of clock pulse #1. The SYNC pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (15.15 MHz) the maximum possible throughput is approximately 195 kHz and not the rated 200 kHz.
t12 t13
EXT DATACLK 0 1
t14
2 3 4 17 18
t1
CS
t15
t19
t10
R/C
t2
BUSY
t16 t17
SYNC
t12 t18 t18
BIT 14 BIT 0 (LSB) BIT 15 (MSB)
DATA
Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/ INT Set to Logic High)
REV. A
-11-
AD974
EXTERNAL CONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion "n-1" can be read during conversion "n" while using a continuous external clock with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK either while CS is high or while both CS and R/C are low. With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock. Use of a continuous clock while a conversion is occurring can increase the DNL and Transition Noise. In Figure 9 a conversion is initiated by taking R/C low with CS held low. While this condition exists a transition of DATACLK, clock pulse #0, will enable the generation of a SYNC pulse. Less then 83 ns after R/C is taken low the BUSY output will go low
t12 t13
EXT DATACLK
to indicate that the conversion process has began. Figure 9 shows R/C then going high and after a delay of greater than 15 ns (t15), clock pulse #1 can be taken high to request the SYNC output. The SYNC output will appear approximately 50 ns after this rising edge and will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid approximately 40 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. Data should be clocked out during the 1st half of BUSY to not degrade conversion performance. This requires use of a 10 MHz DATACLK or greater, with data being read out as soon as the conversion process begins.
t14
0 1 2 3 18
t19
CS
t16
R/C
t15 t1 t20
BUSY
t2 t17 t12 t18 t18
BIT 0 (LSB) BIT 15 (MSB)
SYNC
DATA
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using An External Continuous Data Clock (EXT/ INT Set to Logic High)
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REV. A
AD974
Table I. Analog Input Configuration
Input Voltage Range 10 V 0 V to +5 V 0 V to +4 V
Connect VxA to BIP VIN VIN
Connect VxB to VIN GND VIN
Input Impedance 13.7 k 6.0 k 6.4 k
Table II. Output Codes and Ideal Input Voltage
Description Full-Scale Range Least Significant Bit +Full Scale (FS - 1 LSB) Midscale One LSB Below Midscale -Full Scale 10 V 305 V +9.999695 V 0V -305 V -10 V
Analog Input 0 V to +5 V 76 V +4.999847 V +2.5 V +2.499924 V 0V 0 V to +4 V 61 V +3.999939 V +2 V +1.999939 V 0V
Digital Input Straight Binary
1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000
ANALOG INPUTS
The AD974 is specified to operate with three full-scale analog input ranges. Connections required for each of the eight analog inputs, VxA and VxB and the resulting full-scale ranges, are shown in Table I. The nominal input impedance for each analog input range is also shown. Table II shows the output codes for the ideal input voltages of each of the analog input ranges. The analog input section has a 25 V overvoltage protection on VxA and VxB. Since the AD974 has two analog grounds it is important to ensure that the analog input is referenced to the AGND1 pin, the low current ground. This will minimize any problems associated with a resistive ground drop. It is also important to ensure that the analog inputs are driven by a low impedance source. With its primarily resistive analog input circuitry, the ADC can be driven by a wide selection of general purpose amplifiers. To achieve the low distortion capability of the AD974 care should be taken in the selection of the drive circuitry op amp.
Figure 10 shows the simplified analog input section for the AD974. Since the AD974 can operate with an internal or external reference, and three different analog input ranges, the fullscale analog input range is best represented with a voltage that spans 0 V to VREF across the 40 pF sampling capacitor. The onchip resistors are laser trimmed to ratio match for adjustment of offset and full-scale error using fixed external resistors.
BIP AGND1 REF
4k CAP 3k VxA 12k VxB
2.5V REFERENCE
SWITCHED CAP ADC
40pF 4k AGND2
AD974
Figure 10. Simplified Analog Input
REV. A
-13-
AD974
INPUT RANGE BASIC CONNECTIONS FOR AD974
BIP VxA VIN 10V + 2.2 F VxB AGND1 CAP
AD974
+ REF AGND2
2.2 F
BIP VIN VxA VxB AGND1 0V TO +5V + 2.2 F CAP
AD974
+ REF AGND2
2.2 F
BIP VIN VxA VxB AGND1 CAP
0V TO +4V + 2.2 F
AD974
+ REF AGND2
2.2 F
Figure 11. Analog Input Configurations
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REV. A
AD974
OFFSET AND GAIN ADJUSTMENT
The AD974 is factory trimmed to minimize gain, offset and linearity errors. There are no internal provisions to allow for any further adjustment of offset error through external circuitry. The reference of the AD974 can be adjusted as shown in Figure 12. This will allow the full-scale error of any one channel to be adjusted to zero or will allow the average full-scale error of the four channels to be minimized.
are taken to minimize any degradation in the ADC's performance. Figure 14 shows the load regulation of the reference buffer. Notice that this figure is also normalized so that there is zero error with no dc load. In the linear region, the output impedance at this point is typically 1 . Because of this output impedance, it is important to minimize any ac- or input-dependent loads that will lead to increased distortion. Any dc load will simply act as a gain error. Although the typical characteristic of Figure 14 shows that the AD974 is capable of driving loads greater than 15 mA, it is recommended that the steady state current not exceed 2 mA.
2.2 F +5V 576k 50k
+
CAP
AD974
REF + 2.2 F AGND2
Figure 12. AD974 Full-Scale Trim
VOLTAGE REFERENCE
dV ON CAP PIN - 10nV/DIV
SOURCE CAPABILITY
SINK CAPABILITY
LOAD CURRENT - 5mA/DIV
Figure 14. CAP Pin Load Regulation
Using an External Reference
The AD974 has an on-chip temperature compensated bandgap voltage reference that is factory trimmed to +2.5 V 20 mV. The accuracy of the AD974 over the specified temperature range is dominated by the drift performance of the voltage reference. The on-chip voltage reference is laser-trimmed to provide a typical drift of 7 ppm/C. This typical drift characteristic is shown in Figure 13, which is a plot of the change in reference voltage (in mV) versus the change in temperature--notice the plot is normalized for zero error at +25C. If improved drift performance is required, an external reference such as the AD780 should be used to provide a drift as low as 3 ppm/C. In order to simplify the drive requirements of the voltage reference (internal or external), an on-chip reference buffer is provided.
In addition to the on-chip reference, an external 2.5 V reference can be applied. When choosing an external reference for a 16-bit application, however, careful attention should be paid to noise and temperature drift. These critical specifications can have a significant effect on the ADC performance. Figure 15 shows the AD974 used in bipolar mode with the AD780 voltage reference applied to the REF pin. The AD780 is a bandgap reference that exhibits ultralow drift, low initial error and low output noise. For low power applications, the AD780 provides a low quiescent current, high accuracy and low temperature drift solution.
VIN VxB VxA 0.1 F
3
BIP TEMP VOUT 6 + - - + C3 1F C1 2.2 F AGND1 C4 0.1 F REF
1mV/DIV
AD780
+5V
2
VIN
GND 4
AD974
VANA
-55
25 DEGREES - Celsius
125 C2 2.2 F + -
CAP AGND2
Figure 13. Reference Drift
The output of this buffer is provided at the CAP pin and is available to the user; however, when externally loading the reference buffer, it is important to make sure that proper precautions
Figure 15. External Reference to AD974 Configured for 10 V Input Range
REV. A
-15-
AD974
AC PERFORMANCE
100% 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25 30 35 40 SAMPLES - K 45 50 55 60 66
The AD974 is fully specified and tested for dynamic performance specifications. The ac parameters are required for signal processing applications such as speech recognition and spectrum analysis. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD974 is specified include S/(N+D), THD and Spurious Free Dynamic Range. These terms are discussed in greater detail in the following sections. As a general rule, it is recommended that the results from several conversions be averaged to reduce the effects of noise and thus improve parameters such as S/(N+D) and THD. AC performance can be optimized by operating the ADC at its maximum sampling rate of 200 kHz and digitally filtering the resulting bit stream to the desired signal bandwidth. By distributing noise over a wider frequency range the noise density in the frequency band of interest can be reduced. For example, if the required input bandwidth is 50 kHz, the AD974 could be oversampled by a factor of 4. This would yield a 6 dB improvement in the effective SNR performance.
0 -10 -20 -30 AMPLITUDE - dB -40 -50 -60 -70 -80 -90 -100 -110 -125 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 FREQUENCY - kHz 5280 POINT FFT fSAMPLE = 200kHz fIN = 20kHz SNRD = 86.7dB THD = 100.7dB
Figure 17. INL Plot
100% 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25 30 35 40 SAMPLES - K 45 50 55 60 66
Figure 18. DNL Plot
Figure 16. FFT Plot
DC PERFORMANCE
90 SNR+D (dB) FOR AD974 80 SINAD (dB) FOR VIN = 0dB 70 60 50 40 30 20 10 1 10 100 INPUT SIGNAL FREQUENCY - kHz 1000
The factory calibration scheme used for the AD974 compensates for bit weight errors that may exist in the capacitor array. The mismatch in capacitor values is adjusted (using the calibration coefficients) during a conversion, resulting in excellent dc linearity performance. Figures 17 and 18, respectively, show typical INL and DNL plots for the AD974 at +25C. A histogram test is a statistical method for deriving an A/D converter's differential nonlinearity. A ramp input is sampled by the ADC and a large number of conversions are taken at each voltage level, averaged and then stored. The effect of averaging is to reduce the transition noise by 1/n. If 64 samples are averaged at each point, the effect of transition noise is reduced by a factor of 8; i.e., a transition noise of 0.8 LSBs rms is reduced to 0.1 LSBs rms. Theoretically the codes, during a test of DNL, would all be the same size and therefore have an equal number of occurrences. A code with an average number of occurrences would have a DNL of "0." A code that is different from the average would have a DNL that was either greater or less than zero LSB. A DNL of -1 LSB indicates that there is a missing code present at the 16-bit level and that the ADC exhibits 15-bit performance. -16-
Figure 19. S/(N+D) vs. Input Frequency
REV. A
AD974
110 SFDR 105 -85 -80
SFDR, S/N + D - dB
100
-90 THD - dB
95
-95
When used with an external reference, connected to the REF pin and a 2.2 F capacitor, connected to the CAP pin, the power-up recovery time is typically 1 ms. This typical value of 1 ms for recovery time depends on how much charge has decayed from the external 2.2 F capacitor on the CAP pin and assumes that it has decayed to zero. The 1 ms recovery time has been specified such that settling to 16 bits has been achieved. When used with the internal reference, the dominant time constant for power-up recovery is determined by the external capacitor on the REF pin and the internal 4K impedance seen at that pin. An external 2.2 F capacitor is recommended for the REF pin.
CROSSTALK
90
THD
-100
85
SNRD
-105
80 -75
-50
-25
0 25 50 75 TEMPERATURE - C
100
125
-110 150
Figure 20. AC Parameters vs. Temperature
DC CODE UNCERTAINTY
The crosstalk between adjacent channels, nonadjacent channels and worst-case adjacent channels is shown in Figures 22 to 24. The worst-case crosstalk occurs between channels 1 and 2.
-80 RESULTING AMPLITUDE ON SELECTED CHANNEL (dB) WITH INPUT GROUNDED -85 -90 -95 -100 -105 NONADJACENT CHANNELS
Ideally, a fixed dc input should result in the same output code for repetitive conversions; however, as a consequence of unavoidable circuit noise within the wideband circuits of the ADC, a range of output codes may occur for a given input voltage. Thus, when a dc signal is applied to the AD974 input, and 10,000 conversions are recorded, the result will be a distribution of codes as shown in Figure 21. This histogram shows a bell shaped curve consistent with the Gaussian nature of thermal noise. The histogram is approximately seven codes wide. The standard deviation of this Gaussian distribution results in a code transition noise of 1 LSB rms.
4000
ADJACENT CHANNELS, WORST PAIR
-110
-115 3500 3000 2500 2000 1500 1000 500 dBFS 0 -3 -2 -1 0 1 2 3 4 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 1
1
10 100 1000 ACTIVE CHANNEL INPUT FREQUENCY - kHz
10000
Figure 22. Crosstalk vs. Input Frequency (kHz)
Figure 21. Histogram of 10,000 Conversions of a DC Input
POWER-DOWN FEATURE
The AD974 has analog and reference power-down capability through the PWRD pin. When the PWRD pin is taken high, the power consumption drops from a maximum value of 100 mW to a typical value of 50 W. When in the powerdown mode the previous conversion results are still available in the internal registers and can be read out providing it has not already been shifted out.
2
4
6
8 10 12 FREQUENCY - kHz
14
16
18
20
Figure 23. Adjacent Channel Crosstalk, Worst Pair (8192 Point FFT; AIN 2 = 1.02 kHz, -0.1 dB; AIN 1 = AGND)
REV. A
-17-
AD974
0 -10 -20 -30 -40 -50 dBFS -60 -70 -80 -90 -100 -110 -120 -130 1 2 4 6 8 10 12 FREQUENCY - kHz 14 16 18 20
data read operation. The recommended procedure to ensure this is as follows: * Enable SPORT0 through the System Control register. * Set the SCLK Divide register to zero. * Setup PF0 and PF1 as outputs by setting bits 0 and 1 in PFTYPE. * Force RFS0 low through PF0. The Receive Frame Sync signal has been programmed active high. * Enable AD974 by forcing CS = 0 through PF1. * Enable SPORT0 Receive Interrupt through the IMASK register. * Wait for at least one full conversion cycle of the AD974 and throw away the received data. * Disable the AD974 by forcing CS = 1 through PF1. * Wait for a period of time equal to one conversion cycle. * Force RFS0 high through PF0. * Enable the AD974 by forcing CS = 0 through PF1. The ADSP-2181 SPORT0 will now remain synchronized to the external discontinuous clock for all subsequent conversions.
DR0 SCLK0 DATA DATACLK OSCILLATOR R/C
Figure 24. Adjacent Channel Crosstalk, Worst Pair (8192 Point FFT; AIN 2 = 220 kHz, -0.1 dB; AIN 1 = AGND)
MICROPROCESSOR INTERFACING
The AD974 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD974 is designed to interface with a general purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD974 to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD974 with an SPI equipped microcontroller and the ADSP-2181 signal processor.
SPI INTERFACE
ADSP-2181
PF1 RFS0 PF0
AD974
CS EXT/INT
Figure 25 shows a general interface diagram between the AD974 and an SPI equipped microcontroller. This interface assumes that the convert pulses will originate from the microcontroller and that the AD974 will act as the slave device. The convert pulse could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-ofconversion signal (BUSY going high).
SDI SCK I/O PORT IRQ +5V DATA DATACLK R/C BUSY EXT/INT CS
SPORT0 CNTRL REG = 0 300F
Figure 26. AD974-to-ADSP-2181 Interface
POWER SUPPLIES AND DECOUPLING
AD974
The AD974 has two power supply input pins. VANA and VDIG provide the supply voltages to the analog and digital portions, respectively. VANA is the +5 V supply for the on-chip analog circuitry, and VDIG is the +5 V supply for the on-chip digital circuitry. The AD974 is designed to be independent of power supply sequencing and thus free from supply voltage induced latchup. With high performance linear circuits, changes in the power supplies can result in undesired circuit performance. Optimally, well regulated power supplies should be chosen with less than 1% ripple. The ac output impedance of a power supply is a complex function of frequency and will generally increase with frequency. Thus, high frequency switching, such as that encountered with digital circuitry, requires the fast transient currents that most power supplies cannot adequately provide. Such a situation results in large voltage spikes on the supplies. To compensate for the finite ac output impedance of most supplies, charge "reserves" should be stored in bypass capacitors. This will effectively lower the supplies impedance presented to the AD974 VANA and VDIG pins and reduce the magnitude of these spikes. Decoupling capacitors, typically 0.1 F, should be placed close to the power supply pins of the AD974 to minimize any inductance between the capacitors and the VANA and VDIG pins. REV. A
SPI
Figure 25. AD974-to-SPI Interface
ADSP-2181 INTERFACE
Figure 26 shows an interface between the AD974 and the ADSP-2181 Digital Signal Processor. The AD974 is configured for the Internal Clock mode (EXT/INT = 0) and will therefore act as the master device. The convert command is shown generated from an external oscillator in order to provide a low jitter signal appropriate for both dc and ac measurements. Because the SPORT, within the ADSP-2181, will be seeing a discontinuous external clock, some steps are required to ensure that the serial port is properly synchronized to this clock during each
-18-
AD974
The AD974 may be operated from a single +5 V supply. When separate supplies are used, however, it is beneficial to have larger (10 F) capacitors placed between the logic supply (VDIG ) and digital common (DGND), and between the analog supply (VANA) and the analog common (AGND2). Additionally, 10 F capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. In systems where the device will be subjected to harsh environmental noise, additional decoupling may be required.
GROUNDING BOARD LAYOUT
The AD974 has three ground pins; AGND1, AGND2 and DGND. The analog ground pins are the "high quality" ground reference points and should be connected to the system analog common. AGND2 is the ground to which most internal ADC analog signals are referenced. This ground is most susceptible to current-induced voltage drops and thus must be connected with the least resistance back to the power supply. AGND1 is the low current analog supply ground and should be the analog common for the external reference, input op amp drive circuitry and the input resistor divider circuit. By applying the inputs referenced to this ground, any ground variations will be offset and have a minimal effect on the resulting analog input to the ADC. The digital ground pin, DGND, is the reference point for all of the digital signals that control the AD974. The AD974 can be powered with two separate power supplies or with a single analog supply. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended to connect the analog supply to both the VANA and VDIG pins of the AD974 and the system supply to the remaining digital circuitry. With this configuration, AGND1, AGND2 and DGND should be connected back at the ADC. When there is significant bus activity on the digital output pins, the digital and analog supply pins on the ADC should be separated. This would eliminate any high speed digital noise from coupling back to the analog portion of the AD974. In this configuration, the digital ground pin DGND should be connected to the system digital ground and be separate from the AGND pins.
Designing with high resolution data converters requires careful attention to board layout and trace impedance is a significant issue. A 1.22 mA current through a 0.5 trace will develop a voltage drop of 0.6 mV, which is 2 LSBs at the 16-bit level over the 20 volt full-scale range. Ground circuit impedances should be reduced as much as possible since any ground potential differences between the signal source and the ADC appear as an error voltage in series with the input signal. In addition to ground drops, inductive and capacitive coupling needs to be considered. This is especially true when high accuracy analog input signals share the same board with digital signals. Thus, to minimize input noise coupling, the input signal leads to VIN and the signal return leads from AGND should be kept as short as possible. In addition, power supplies should also be decoupled to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire and ground planes are highly recommended to provide low impedance signal paths. Separate analog and digital ground planes are also recommended with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from high speed digital signals and if absolutely necessary, should only cross them at right angles. In addition, it is recommended that multilayer PC boards be used with separate power and ground planes. When designing the separate sections, careful attention should be paid to the layout.
REV. A
-19-
AD974
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead 300 Mil Plastic DIP (N-28B)
C3273a-0-5/99
0.195 (4.95) 0.115 (2.93) 0.014 (0.356) 0.008 (0.204) 0.0500 (1.27) 0.0157 (0.40) 0.03 (0.762) 0.022 (0.558) 1.425 (38.195) 1.385 (35.179)
28 1 15 14
0.280 (7.11) 0.240 (6.10)
PIN 1 0.210 (5.33) MAX SEATING PLANE 0.022 (0.558) 0.100 (2.54) 0.070 (1.77) BSC 0.014 (0.356) 0.045 (1.15) 0.015 (0.381) MIN 0.150 (3.81) 0.115 (2.92)
0.325 (8.25) 0.300 (7.62)
28-Lead Wide Body (SOIC) (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
8 0
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
0.078 (1.98) 0.068 (1.73)
PIN 1
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING PLANE
0.009 (0.229) 0.005 (0.127)
8 0
-20-
REV. A
PRINTED IN U.S.A.
1
14
0.212 (5.38) 0.205 (5.21)

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